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Freescale Semiconductor
Technical Data
MPC755EC Rev. 6.1, 01/2005
MPC755 RISC Microprocessor Hardware Specifications
This document is primarily concerned with the MPC755; however, unless otherwise noted, all information here also applies to the MPC745. The MPC755 and MPC745 are PowerPCTM microprocessors. The MPC755 and MPC745 are reduced instruction set computing (RISC) microprocessors that implement the PowerPC instruction set architecture. This document describes pertinent physical characteristics of the MPC755. For functional characteristics of the processor, refer to the MPC750 RISC Microprocessor Family User's Manual. To locate any published errata or updates for this document, refer to the website at http://www.freescale.com.
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. Contents Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical and Thermal Characteristics . . . . . . . . . . . . 7 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Pinout Listings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Package Description . . . . . . . . . . . . . . . . . . . . . . . . . 31 System Design Information . . . . . . . . . . . . . . . . . . . 36 Document Revision History . . . . . . . . . . . . . . . . . . . 50 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 52
(c) Freescale Semiconductor, Inc., 2004. All rights reserved.
Overview
1
Overview
The MPC755 is targeted for low-cost, low-power systems and supports the following power management features--doze, nap, sleep, and dynamic power management. The MPC755 consists of a processor core and an internal L2 tag combined with a dedicated L2 cache interface and a 60x bus. The MPC745 is identical to the MPC755 except it does not support the L2 cache interface. Figure 1 shows a block diagram of the MPC755.
MPC755 RISC Microprocessor Hardware Specifications, Rev. 6.1 2 Freescale Semiconductor
Instruction Unit
Fetcher BTIC 64-Entry BHT ITLB SRs (Shadow) IBAT Array CTR LR Tags
Freescale Semiconductor Branch Processing Unit Instruction MMU
128-Bit (4 Instructions) Instruction Queue (6-Word) 32-Kbyte I Cache Dispatch Unit 64-Bit (2 Instructions) Reservation Station GPR File Rename Buffers (6) 32-Bit Load/Store Unit Reservation Station Reservation Station (2-Entry) FPR File Rename Buffers (6) 64-Bit Reservation Station Integer Unit 2 System Register Unit 64-Bit
Additional Features
* Time Base Counter/Decrementer * Clock Multiplier * JTAG/COP Interface * Thermal/Power Management * Performance Monitor
2 Instructions
Reservation Station
Integer Unit 1
+
(EA Calculation) Store Queue
Floating-Point Unit
+x/ +
CR 32-Bit
+x/
FPSCR FPSCR
Figure 1. MPC755 Block Diagram
PA
Data MMU SRs (Original) DBAT Array DTLB
32-Bit
EA
60x Bus Interface Unit 64-Bit Instruction Fetch Queue L1 Castout Queue Tags 32-Kbyte D Cache Data Load Queue L2 Bus Interface Unit
L2 Castout Queue
MPC755 RISC Microprocessor Hardware Specifications, Rev. 6.1
32-Bit Address Bus 32-/64-Bit Data Bus 17-Bit L2 Address Bus 64-Bit L2 Data Bus
Completion Unit
Reorder Buffer (6-Entry)
L2 Controller L2CR L2 Tags
Not in the MPC745 Overview
3
Features
2
*
Features
Branch processing unit -- Four instructions fetched per clock -- One branch processed per cycle (plus resolving two speculations) -- Up to one speculative stream in execution, one additional speculative stream in fetch -- 512-entry branch history table (BHT) for dynamic prediction -- 64-entry, four-way set-associative branch target instruction cache (BTIC) for eliminating branch delay slots * Dispatch unit -- Full hardware detection of dependencies (resolved in the execution units) -- Dispatch two instructions to six independent units (system, branch, load/store, fixed-point unit 1, fixed-point unit 2, floating-point) -- Serialization control (predispatch, postdispatch, execution serialization) * Decode -- Register file access -- Forwarding control -- Partial instruction decode * Completion -- Six-entry completion buffer -- Instruction tracking and peak completion of two instructions per cycle -- Completion of instructions in program order while supporting out-of-order instruction execution, completion serialization, and all instruction flow changes * Fixed point units (FXUs) that share 32 GPRs for integer operands -- Fixed Point Unit 1 (FXU1)--multiply, divide, shift, rotate, arithmetic, logical -- Fixed Point Unit 2 (FXU2)--shift, rotate, arithmetic, logical -- Single-cycle arithmetic, shifts, rotates, logical -- Multiply and divide support (multi-cycle) -- Early out multiply * Floating-point unit and a 32-entry FPR file -- Support for IEEE standard 754 single- and double-precision floating-point arithmetic -- Hardware support for divide -- Hardware support for denormalized numbers -- Single-entry reservation station -- Supports non-IEEE mode for time-critical operations -- Three-cycle latency, one-cycle throughput, single-precision multiply-add -- Three-cycle latency, one-cycle throughput, double-precision add
MPC755 RISC Microprocessor Hardware Specifications, Rev. 6.1
This section summarizes features of the MPC755 implementation of the PowerPC architecture. Major features of the MPC755 are as follows:
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Freescale Semiconductor
Features
-- Four-cycle latency, two-cycle throughput, double-precision multiply-add * System unit -- Executes CR logical instructions and miscellaneous system instructions -- Special register transfer instructions * Load/store unit -- One-cycle load or store cache access (byte, half-word, word, double word) -- Effective address generation -- Hits under misses (one outstanding miss) -- Single-cycle unaligned access within double-word boundary -- Alignment, zero padding, sign extend for integer register file -- Floating-point internal format conversion (alignment, normalization) -- Sequencing for load/store multiples and string operations -- Store gathering -- Cache and TLB instructions -- Big- and little-endian byte addressing supported * Level 1 cache structure -- 32K, 32-byte line, eight-way set-associative instruction cache (iL1) -- 32K, 32-byte line, eight-way set-associative data cache (dL1) -- Cache locking for both instruction and data caches, selectable by group of ways -- Single-cycle cache access -- Pseudo least-recently-used (PLRU) replacement -- Copy-back or write-through data cache (on a page per page basis) -- MEI data cache coherency maintained in hardware -- Nonblocking instruction and data cache (one outstanding miss under hits) -- No snooping of instruction cache * Level 2 (L2) cache interface (not implemented on MPC745) -- Internal L2 cache controller and tags; external data SRAMs -- 256K, 512K, and 1 Mbyte two-way set-associative L2 cache support -- Copy-back or write-through data cache (on a page basis, or for all L2) -- Instruction-only mode and data-only mode -- 64-byte (256K/512K) or 128-byte (1M) sectored line size -- Supports flow through (register-buffer) synchronous BurstRAMs, pipelined (register-register) synchronous BurstRAMs (3-1-1-1 or strobeless 4-1-1-1) and pipelined (register-register) late write synchronous BurstRAMs -- L2 configurable to cache, private memory, or split cache/private memory -- Core-to-L2 frequency divisors of /1, /1.5, /2, /2.5, and /3 supported -- 64-bit data bus -- Selectable interface voltages of 2.5 and 3.3 V
MPC755 RISC Microprocessor Hardware Specifications, Rev. 6.1 Freescale Semiconductor 5
General Parameters
-- Parity checking on both L2 address and data * Memory management unit -- 128-entry, two-way set-associative instruction TLB -- 128-entry, two-way set-associative data TLB -- Hardware reload for TLBs -- Hardware or optional software tablewalk support -- Eight instruction BATs and eight data BATs -- Eight SPRGs, for assistance with software tablewalks -- Virtual memory support for up to 4 exabytes (252) of virtual memory -- Real memory support for up to 4 gigabytes (232) of physical memory * Bus interface -- Compatible with 60x processor interface -- 32-bit address bus -- 64-bit data bus, 32-bit mode selectable -- Bus-to-core frequency multipliers of 2x, 3x, 3.5x, 4x, 4.5x, 5x, 5.5x, 6x, 6.5x, 7x, 7.5x, 8x, 10x supported -- Selectable interface voltages of 2.5 and 3.3 V -- Parity checking on both address and data buses * Power management -- Low-power design with thermal requirements very similar to MPC740/MPC750 -- Three static power saving modes: doze, nap, and sleep -- Dynamic power management * Integrated thermal management assist unit -- On-chip thermal sensor and control logic -- Thermal management interrupt for software regulation of junction temperature * Testability -- LSSD scan design -- IEEE 1149.1 JTAG interface
3
General Parameters
Technology Die size Transistor count Logic design Packages 0.22 m CMOS, six-layer metal 6.61 mm x 7.73 mm (51 mm2) 6.75 million Fully-static MPC745: Surface mount 255 plastic ball grid array (PBGA) MPC755: Surface mount 360 ceramic ball grid array (CBGA) Surface mount 360 plastic ball grid array (PBGA)
MPC755 RISC Microprocessor Hardware Specifications, Rev. 6.1
The following list provides a summary of the general parameters of the MPC755:
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Freescale Semiconductor
Electrical and Thermal Characteristics
Core power supply I/O power supply
2.0 V 100 mV DC (nominal; some parts support core voltages down to 1.8 V; see Table 3 for recommended operating conditions) 2.5 V 100 mV DC or 3.3 V 165 mV DC (input thresholds are configuration pin selectable)
4
4.1
Electrical and Thermal Characteristics
DC Electrical Characteristics
Table 1. Absolute Maximum Ratings1
Characteristic Core supply voltage PLL supply voltage L2 DLL supply voltage Processor bus supply voltage L2 bus supply voltage Input voltage Processor bus L2 bus JTAG signals Storage temperature range Symbol VDD AVDD L2AVDD OVDD L2OVDD Vin Vin Vin Tstg Maximum Value -0.3 to 2.5 -0.3 to 2.5 -0.3 to 2.5 -0.3 to 3.6 -0.3 to 3.6 -0.3 to OVDD + 0.3 V -0.3 to L2OVDD + 0.3 V -0.3 to 3.6 -55 to 150 Unit V V V V V V V V C Notes 4 4 4 3 3 2, 5 2, 5
This section provides the AC and DC electrical specifications and thermal characteristics for the MPC755.
Table 1 through Table 7 describe the MPC755 DC electrical characteristics. Table 1 provides the absolute maximum ratings.
Notes: 1. Functional and tested operating conditions are given in Table 3. Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. Caution: Vin must not exceed OVDD or L2OVDD by more than 0.3 V at any time including during power-on reset. 3. Caution: L2OVDD/OVDD must not exceed VDD/AVDD/L2AVDD by more than 1.6 V during normal operation. During power-on reset and power-down sequences, L2OVDD/OVDD may exceed VDD/AVDD/L2AVDD by up to 3.3 V for up to 20 ms, or by 2.5 V for up to 40 ms. Excursions beyond 3.3 V or 40 ms are not supported. 4. Caution: VDD/AVDD/L2AVDD must not exceed L2OVDD/OVDD by more than 0.4 V during normal operation. During power-on reset and power-down sequences, VDD/AVDD/L2AVDD may exceed L2OVDD/OVDD by up to 1.0 V for up to 20 ms, or by 0.7 V for up to 40 ms. Excursions beyond 1.0 V or 40 ms are not supported. 5. This is a DC specifications only. Vin may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2.
MPC755 RISC Microprocessor Hardware Specifications, Rev. 6.1 Freescale Semiconductor 7
Electrical and Thermal Characteristics
Figure 2 shows the allowable undershoot and overshoot voltage on the MPC755.
(L2)OVDD + 20% (L2)OVDD + 5% (L2)OVDD
VIH
VIL GND GND - 0.3 V GND - 0.7 V
Not to Exceed 10% of tSYSCLK
Figure 2. Overshoot/Undershoot Voltage
The MPC755 provides several I/O voltages to support both compatibility with existing systems and migration to future systems. The MPC755 core voltage must always be provided at nominal 2.0 V (see Table 3 for actual recommended core voltage). Voltage to the L2 I/Os and processor interface I/Os are provided through separate sets of supply pins and may be provided at the voltages shown in Table 2. The input voltage threshold for each bus is selected by sampling the state of the voltage select pins BVSEL and L2VSEL during operation. These signals must remain stable during part operation and cannot change. The output voltage will swing from GND to the maximum voltage applied to the OVDD or L2OVDD power pins. Table 2 describes the input threshold voltage setting.
Table 2. Input Threshold Voltage Setting
Part Revision E BVSEL Signal 0 1 Processor Bus Interface Voltage Not Available 2.5 V/3.3 V L2VSEL Signal 0 1 L2 Bus Interface Voltage Not Available 2.5 V/3.3 V
Caution: The input threshold selection must agree with the OVDD/L2OVDD voltages supplied. Note: The input threshold settings above are different for all revisions prior to Rev. 2.8 (Rev. E). For more information, refer to Section 10.2, "Part Numbers Not Fully Addressed by This Document."
MPC755 RISC Microprocessor Hardware Specifications, Rev. 6.1 8 Freescale Semiconductor
Electrical and Thermal Characteristics
Table 3 provides the recommended operating conditions for the MPC755.
Table 3. Recommended Operating Conditions 1
Recommended Value Characteristic Symbol 300 MHz, 350 MHz Min Core supply voltage PLL supply voltage L2 DLL supply voltage Processor bus supply voltage L2 bus supply voltage Input voltage BVSEL = 1 VDD AVDD L2AVDD OVDD 1.80 1.80 1.80 2.375 3.135 L2VSEL = 1 L2OVDD 2.375 3.135 Processor bus L2 bus JTAG signals Die-junction temperature Vin Vin Vin Tj GND GND GND 0 Max 2.10 2.10 2.10 2.625 3.465 2.625 3.465 OVDD L2OVDD OVDD 105 Min 1.90 1.90 1.90 2.375 3.135 2.375 3.135 GND GND GND 0 400 MHz Max 2.10 2.10 2.10 2.625 3.465 2.625 3.465 OVDD L2OVDD OVDD 105 V V V C V V V V V 3 3 3 2, 4 5 2, 4 5 Unit Notes
Notes: 1. These are the recommended and tested operating conditions. Proper device operation outside of these conditions is not guaranteed. 2. Revisions prior to Rev. 2.8 (Rev. E) offered different I/O voltage support. For more information, refer to Section 10.2, "Part Numbers Not Fully Addressed by This Document." 3. 2.0 V nominal. 4. 2.5 V nominal. 5. 3.3 V nominal.
Table 4 provides the package thermal characteristics for the MPC755 and MPC745. The MPC755 was initially sampled in a CBGA package, but production units are currently provided in both a CBGA and a PBGA package. Because of the better long-term device-to-board interconnect reliability of the PBGA package, Freescale recommends use of a PBGA package except where circumstances dictate use of a CBGA package. The MPC745 is offered in a PBGA package only.
MPC755 RISC Microprocessor Hardware Specifications, Rev. 6.1 Freescale Semiconductor 9
Electrical and Thermal Characteristics
Table 4. Package Thermal Characteristics 6
Value Characteristic Symbol MPC755 CBGA 24 17 18 14 8 <0.1 MPC755 PBGA 31 25 25 21 17 <0.1 MPC745 PBGA 34 26 27 22 17 <0.1 Unit Notes
Junction-to-ambient thermal resistance, natural convection Junction-to-ambient thermal resistance, natural convection, four-layer (2s2p) board Junction-to-ambient thermal resistance, 200 ft/min airflow, single-layer (1s) board Junction-to-ambient thermal resistance, 200 ft/min airflow, four-layer (2s2p) board Junction-to-board thermal resistance Junction-to-case thermal resistance
RJA RJMA RJMA RJMA RJB RJC
C/W C/W C/W C/W C/W C/W
1, 2 1, 3 1, 3 1, 3 4 5
Notes: 1. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal. 3. Per JEDEC JESD51-6 with the board horizontal. 4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1) with the calculated case temperature. The actual value of RJC for the part is less than 0.1C/W. 6. Refer to Section 8.8, "Thermal Management Information," for more details about thermal management.
The MPC755 incorporates a thermal management assist unit (TAU) composed of a thermal sensor, digital-to-analog converter, comparator, control logic, and dedicated special-purpose registers (SPRs). See the MPC750 RISC Microprocessor Family User's Manual for more information on the use of this feature. Specifications for the thermal sensor portion of the TAU are found in Table 5.
MPC755 RISC Microprocessor Hardware Specifications, Rev. 6.1 10 Freescale Semiconductor
Electrical and Thermal Characteristics
Table 5. Thermal Sensor Specifications
At recommended operating conditions (see Table 3)
Characteristic Temperature range Comparator settling time Resolution Accuracy
Min 0 20 4 -12
Max 127 -- -- +12
Unit C s C C
Notes 1 2, 3 3 3
Notes: 1. The temperature is the junction temperature of the die. The thermal assist unit's raw output does not indicate an absolute temperature, but must be interpreted by software to derive the absolute junction temperature. For information about the use and calibration of the TAU, see Freescale Application Note AN1800/D, Programming the Thermal Assist Unit in the MPC750 Microprocessor. 2. The comparator settling time value must be converted into the number of CPU clocks that need to be written into the THRM3 SPR. 3. Guaranteed by design and characterization.
Table 6 provides the DC electrical characteristics for the MPC755.
Table 6. DC Electrical Specifications
At recommended operating conditions (see Table 3)
Characteristic Input high voltage (all inputs except SYSCLK)
Nominal Bus Voltage
1
Symbol VIH VIH VIL VIL KVIH KVIH KVIL KVIL Iin ITSI
Min 1.6 2.0 -0.3 -0.3 1.8 2.4 -0.3 -0.3 -- -- 1.7 2.4 -- --
Max (L2)OVDD + 0.3 (L2)OVDD + 0.3 0.6 0.8 OVDD + 0.3 OVDD + 0.3 0.4 0.4 10 10 -- -- 0.45 0.4
Unit V V V V V V V V A A V V V V
Notes 2, 3 2, 3 2
2.5 3.3
Input low voltage (all inputs except SYSCLK)
2.5 3.3
SYSCLK input high voltage
2.5 3.3
SYSCLK input low voltage
2.5 3.3
Input leakage current, Vin = L2OVDD/OVDD High-Z (off-state) leakage current, Vin = L2OVDD/OVDD Output high voltage, IOH = -6 mA 2.5 3.3 Output low voltage, IOL = 6 mA 2.5 3.3
2, 3 2, 3, 5
VOH VOH VOL VOL
MPC755 RISC Microprocessor Hardware Specifications, Rev. 6.1 Freescale Semiconductor 11
Electrical and Thermal Characteristics
Table 6. DC Electrical Specifications (continued)
At recommended operating conditions (see Table 3)
Characteristic Capacitance, Vin = 0 V, f = 1 MHz
Nominal Bus Voltage
1
Symbol Cin
Min --
Max 5.0
Unit pF
Notes 3, 4
Notes: 1. Nominal voltages; see Table 3 for recommended operating conditions. 2. For processor bus signals, the reference is OVDD while L2OVDD is the reference for the L2 bus signals. 3. Excludes test signals (LSSD_MODE, L1_TSTCLK, L2_TSTCLK) and IEEE 1149.1 boundary scan (JTAG) signals. 4. Capacitance is periodically sampled rather than 100% tested. 5. The leakage is measured for nominal OVDD and VDD, or both OVDD and VDD must vary in the same direction (for example, both OVDD and VDD vary by either +5% or -5%).
Table 7 provides the power consumption for the MPC755.
Table 7. Power Consumption for MPC755
Processor (CPU) Frequency 300 MHz 350 MHz Full-Power Mode Typical Maximum 3.1 4.5 Doze Mode Maximum 1.8 Nap Mode Maximum 1.0 1.0 Sleep Mode Maximum 550 550 550 mW 1, 2, 4 1.0 W 1, 2, 4 2.0 2.3 W 1, 2, 4 3.6 5.3 5.4 8.0 W W 1, 3, 4 1, 2 400 MHz Unit Notes
Sleep Mode (PLL and DLL Disabled) Maximum 510 510 510 mW 1, 2
Notes: 1. These values apply for all valid processor bus and L2 bus ratios. The values do not include I/O supply power (OVDD and L2OVDD) or PLL/DLL supply power (AVDD and L2AVDD). OVDD and L2OVDD power is system dependent, but is typically <10% of VDD power. Worst case power consumption for AVDD = 15 mW and L2AVDD = 15 mW. 2. Maximum power is measured at nominal VDD (see Table 3) while running an entirely cache-resident, contrived sequence of instructions which keep the execution units maximally busy. 3. Typical power is an average value measured at the nominal recommended VDD (see Table 3) and 65C in a system while running a typical code sequence. 4. Not 100% tested. Characterized and periodically sampled.
MPC755 RISC Microprocessor Hardware Specifications, Rev. 6.1 12 Freescale Semiconductor
Electrical and Thermal Characteristics
4.2
AC Electrical Characteristics
This section provides the AC electrical characteristics for the MPC755. After fabrication, functional parts are sorted by maximum processor core frequency as shown in Section 4.2.1, "Clock AC Specifications," and tested for conformance to the AC specifications for that frequency. The processor core frequency is determined by the bus (SYSCLK) frequency and the settings of the PLL_CFG[0:3] signals. Parts are sold by maximum processor core frequency; see Section 10, "Ordering Information."
4.2.1
Clock AC Specifications
Table 8. Clock AC Timing Specifications
Table 8 provides the clock AC timing specifications as defined in Figure 3.
At recommended operating conditions (see Table 3)
Maximum Processor Core Frequency Characteristic Symbol 300 MHz Min Processor frequency VCO frequency SYSCLK frequency SYSCLK cycle time SYSCLK rise and fall time fcore fVCO fSYSCLK tSYSCLK tKR, tKF tKR, tKF SYSCLK duty cycle measured at OVDD/2 SYSCLK jitter Internal PLL relock time tKHKL/ tSYSCLK 200 400 25 10 -- -- 40 -- -- Max 300 600 100 40 2.0 1.4 60 150 100 350 MHz Min 200 400 25 10 -- -- 40 -- -- Max 350 700 100 40 2.0 1.4 60 150 100 400 MHz Min 200 400 25 10 -- -- 40 -- -- Max 400 800 100 40 2.0 1.4 60 150 100 MHz MHz MHz ns ns ns % ps s 2 2 3 3, 4 3, 5 1 1 1 Unit Notes
Notes: 1. Caution: The SYSCLK frequency and PLL_CFG[0:3] settings must be chosen such that the resulting SYSCLK (bus) frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum operating frequencies. Refer to the PLL_CFG[0:3] signal description in Section 8.1, "PLL Configuration," for valid PLL_CFG[0:3] settings. 2. Rise and fall times measurements are now specified in terms of slew rates, rather than time to account for selectable I/O bus interface levels. The minimum slew rate of 1 V/ns is equivalent to a 2 ns maximum rise/fall time measured at 0.4 and 2.4 V (OVDD = 3.3 V) or a rise/fall time of 1 ns measured at 0.4 and 1.8 V (OVDD = 2.5 V). 3. Timing is guaranteed by design and characterization. 4. This represents total input jitter--short term and long term combined--and is guaranteed by design. 5. Relock timing is guaranteed by design and characterization. PLL-relock time is the maximum amount of time required for PLL lock after a stable VDD and SYSCLK are reached during the power-on reset sequence. This specification also applies when the PLL has been disabled and subsequently re-enabled during sleep mode. Also note that HRESET must be held asserted for a minimum of 255 bus clocks after the PLL-relock time during the power-on reset sequence.
MPC755 RISC Microprocessor Hardware Specifications, Rev. 6.1 Freescale Semiconductor 13
Electrical and Thermal Characteristics
Figure 3 provides the SYSCLK input timing diagram.
SYSCLK VM tKHKL tSYSCLK VM = Midpoint Voltage (OVDD/2) VM VM tKR KVIH KVIL tKF
Figure 3. SYSCLK Input Timing Diagram
4.2.2
Processor Bus AC Specifications
Table 9 provides the processor bus AC timing specifications for the MPC755 as defined in Figure 4 and Figure 6. Timing specifications for the L2 bus are provided in Section 4.2.3, "L2 Clock AC Specifications."
Table 9. Processor Bus Mode Selection AC Timing Specifications 1
At recommended operating conditions (see Table 3)
Parameter Mode select input setup to HRESET HRESET to mode select input hold
Symbol 2 tMVRH tMXRH
All Speed Grades Unit Min 8 0 Max -- -- tsysclk ns 3, 4, 5, 6, 7 3, 4, 6, 7, 8 Notes
Notes: 1. All input specifications are measured from the midpoint of the signal in question to the midpoint of the rising edge of the input SYSCLK. All output specifications are measured from the midpoint of the rising edge of SYSCLK to the midpoint of the signal in question. All output timings assume a purely resistive 50- load (see Figure 5). Input and output timings are measured at the pin; time-of-flight delays must be added for trace lengths, vias, and connectors in the system. 2. The symbology used for timing specifications herein follows the pattern of t(signal)(state)(reference)(state) for inputs and t(reference)(state)(signal)(state) for outputs. For example, tIVKH symbolizes the time input signals (I) reach the valid state (V) relative to the SYSCLK reference (K) going to the high (H) state or input setup time. And tKHOV symbolizes the time from SYSCLK (K) going high (H) until outputs (O) are valid (V) or output valid time. Input hold time can be read as the time that the input signal (I) went invalid (X) with respect to the rising clock edge (KH)--note the position of the reference and its state for inputs--and output hold time can be read as the time from the rising edge (KH) until the output went invalid (OX). 3. The setup and hold time is with respect to the rising edge of HRESET (see Figure 4). 4. This specification is for configuration mode select only. Also note that the HRESET must be held asserted for a minimum of 255 bus clocks after the PLL-relock time during the power-on reset sequence. 5. tsysclk is the period of the external clock (SYSCLK) in ns. The numbers given in the table must be multiplied by the period of SYSCLK to compute the actual time duration (in ns) of the parameter in question. 6. Mode select signals are BVSEL, L2VSEL, PLL_CFG[0:3], and TLBISYNC. 7. Guaranteed by design and characterization. 8. Bus mode select pins must remain stable during operation. Changing the logic states of BVSEL or L2VSEL during operation will cause the bus mode voltage selection to change. Changing the logic states of the PLL_CFG pins during operation will cause the PLL division ratio selection to change. Both of these conditions are considered outside the specification and are not supported. Once HRESET is negated the states of the bus mode selection pins must remain stable.
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Electrical and Thermal Characteristics
Figure 4 provides the mode select input timing diagram for the MPC755.
HRESET tMVRH Mode Signals VM = Midpoint Voltage (OVDD/2) VM tMXRH
Figure 4. Mode Input Timing Diagram
Figure 5 provides the AC test load for the MPC755.
Output Z0 = 50 OVDD/2
RL = 50
Figure 5. AC Test Load Table 10. Processor Bus AC Timing Specifications 1
At recommended operating conditions (see Table 3)
All Speed Grades Parameter Setup times: All inputs Input hold times: TLBISYNC, MCP, SMI Input hold times: All inputs, except TLBISYNC, MCP, SMI Valid times: All outputs Output hold times: All outputs SYSCLK to output enable SYSCLK to output high impedance (all except ABB, ARTRY, DBB) SYSCLK to ABB, DBB high impedance after precharge Maximum delay to ARTRY precharge Symbol Min tIVKH tIXKH tIXKH tKHOV tKHOX tKHOE tKHOZ tKHABPZ tKHARP 2.5 0.6 0.2 -- 1.0 0.5 -- -- -- Max -- -- -- 4.1 -- -- 6.0 1.0 1 ns ns ns ns ns ns ns tsysclk tsysclk 2 2 2, 3, 4 2, 3, 5 6 6 Unit Notes
MPC755 RISC Microprocessor Hardware Specifications, Rev. 6.1 Freescale Semiconductor 15
Electrical and Thermal Characteristics
Table 10. Processor Bus AC Timing Specifications 1 (continued)
At recommended operating conditions (see Table 3)
All Speed Grades Parameter SYSCLK to ARTRY high impedance after precharge Symbol Min tKHARPZ -- Max 2 tsysclk 2, 3, 5 Unit Notes
Notes: 1. Revisions prior to Rev. 2.8 (Rev. E) were limited in performance and did not conform to this specification. For more information, refer to Section 10.2, "Part Numbers Not Fully Addressed by This Document." 2. Guaranteed by design and characterization. 3. tsysclk is the period of the external clock (SYSCLK) in ns. The numbers given in the table must be multiplied by the period of SYSCLK to compute the actual time duration (in ns) of the parameter in question. 4. Per the 60x bus protocol, TS, ABB, and DBB are driven only by the currently active bus master. They are asserted low, then precharged high before returning to high-Z as shown in Figure 6. The nominal precharge width for TS, ABB, or DBB is 0.5 x tsysclk, that is, less than the minimum tsysclk period, to ensure that another master asserting TS, ABB, or DBB on the following clock will not contend with the precharge. Output valid and output hold timing is tested for the signal asserted. Output valid time is tested for precharge. The high-Z behavior is guaranteed by design. 5. Per the 60x bus protocol, ARTRY can be driven by multiple bus masters through the clock period immediately following AACK. Bus contention is not an issue since any master asserting ARTRY will be driving it low. Any master asserting it low in the first clock following AACK will then go to high-Z for one clock before precharging it high during the second cycle after the assertion of AACK. The nominal precharge width for ARTRY is 1.0 tsysclk; that is, it should be high-Z as shown in Figure 6 before the first opportunity for another master to assert ARTRY. Output valid and output hold timing is tested for the signal asserted. Output valid time is tested for precharge. The high-Z and precharge behavior is guaranteed by design. 6. MCP and SRESET must be held asserted for a minimum of two bus clock cycles; INT and SMI should be held asserted until the exception is taken; CKSTP_IN must be held asserted until the system has been reset. See the MPC750 RISC Microprocessor Family User's Manual for more information.
MPC755 RISC Microprocessor Hardware Specifications, Rev. 6.1 16 Freescale Semiconductor
Electrical and Thermal Characteristics
Figure 6 provides the input/output timing diagram for the MPC755.
SYSCLK VM tIVKH All Inputs tKHOE All Outputs (Except TS, ABB, ARTRY, DBB) tKHOV tKHOX tKHOZ VM tIXKH VM
tKHOV tKHOV
tKHABPZ tKHOZ tKHOX
TS, ABB, DBB
tKHARPZ tKHOV ARTRY tKHARP tKHOX VM = Midpoint Voltage (OVDD/2 or Vin/2) tKHOV
Figure 6. Input/Output Timing Diagram
4.2.3
L2 Clock AC Specifications
The L2CLK frequency is programmed by the L2 configuration register (L2CR[4-6]) core-to-L2 divisor ratio. See Table 17 for example core and L2 frequencies at various divisors. Table 11 provides the potential range of L2CLK output AC timing specifications as defined in Figure 7. The minimum L2CLK frequency of Table 11 is specified by the maximum delay of the internal DLL. The variable-tap DLL introduces up to a full clock period delay in the L2CLK_OUTA, L2CLK_OUTB, and L2SYNC_OUT signals so that the returning L2SYNC_IN signal is phase-aligned with the next core clock (divided by the L2 divisor ratio). Do not choose a core-to-L2 divisor which results in an L2 frequency below this minimum, or the L2CLK_OUT signals provided for SRAM clocking will not be phase-aligned with the MPC755 core clock at the SRAMs. The maximum L2CLK frequency shown in Table 11 is the core frequency divided by one. Very few L2 SRAM designs will be able to operate in this mode, especially at higher core frequencies. Therefore, most designs will select a greater core-to-L2 divisor to provide a longer L2CLK period for read and write access to the L2 SRAMs. The maximum L2CLK frequency for any application of the MPC755 will be a function of the AC timings of the MPC755, the AC timings for the SRAM, bus loading, and printed-circuit board trace length. The current AC timing of the MPC755 supports up to 200 MHz with typical, similarly-rated SRAM parts, provided careful design practices are observed. Clock trace lengths must be matched and all trace lengths should be as short as possible. Higher frequencies can be achieved by using better performing SRAM. Note that revisions of the MPC755 prior to Rev. 2.8 (Rev. E) were limited in performance, and were typically limited to 175 MHz with similarly-rated SRAM. For more information, see Section 10.2, "Part Numbers Not Fully Addressed by This Document."
MPC755 RISC Microprocessor Hardware Specifications, Rev. 6.1 Freescale Semiconductor 17
Electrical and Thermal Characteristics
Freescale is similarly limited by system constraints and cannot perform tests of the L2 interface on a socketed part on a functional tester at the maximum frequencies of Table 11. Therefore, functional operation and AC timing information are tested at core-to-L2 divisors of 2 or greater. Functionality of core-to-L2 divisors of 1 or 1.5 is verified at less than maximum rated frequencies. L2 input and output signals are latched or enabled, respectively, by the internal L2CLK (which is SYSCLK multiplied up to the core frequency and divided down to the L2CLK frequency). In other words, the AC timings of Table 12 and Table 13 are entirely independent of L2SYNC_IN. In a closed loop system, where L2SYNC_IN is driven through the board trace by L2SYNC_OUT, L2SYNC_IN only controls the output phase of L2CLK_OUTA and L2CLK_OUTB which are used to latch or enable data at the SRAMs. However, since in a closed loop system L2SYNC_IN is held in phase alignment with the internal L2CLK, the signals of Table 12 and Table 13 are referenced to this signal rather than the not-externally-visible internal L2CLK. During manufacturing test, these times are actually measured relative to SYSCLK. The L2SYNC_OUT signal is intended to be routed halfway out to the SRAMs and then returned to the L2SYNC_IN input of the MPC755 to synchronize L2CLK_OUT at the SRAM with the processor's internal clock. L2CLK_OUT at the SRAM can be offset forward or backward in time by shortening or lengthening the routing of L2SYNC_OUT to L2SYNC_IN. See Freescale Application Note AN1794/D, Backside L2 Timing Analysis for PCB Design Engineers. The L2CLK_OUTA and L2CLK_OUTB signals should not have more than two loads.
Table 11. L2CLK Output AC Timing Specification
At recommended operating conditions (see Table 3)
Parameter L2CLK frequency L2CLK cycle time L2CLK duty cycle Internal DLL-relock time DLL capture window L2CLK_OUT output-to-output skew L2CLK_OUT output jitter
Symbol fL2CLK tL2CLK tCHCL/tL2CLK
All Speed Grades Min 80 2.5 45 640 0 Max 450 12.5 55 -- 10 50 150
Unit MHz ns % L2CLK ns ps ps
Notes 1, 4 2, 7 3, 7 5, 7 6, 7 6, 7
tL2CSKW
-- --
Notes: 1. L2CLK outputs are L2CLK_OUTA, L2CLK_OUTB, L2CLK_OUT, and L2SYNC_OUT pins. The L2CLK frequency-to-core frequency settings must be chosen such that the resulting L2CLK frequency and core frequency do not exceed their respective maximum or minimum operating frequencies. The maximum L2LCK frequency will be system dependent. L2CLK_OUTA and L2CLK_OUTB must have equal loading. 2. The nominal duty cycle of the L2CLK is 50% measured at midpoint voltage. 3. The DLL-relock time is specified in terms of L2CLK periods. The number in the table must be multiplied by the period of L2CLK to compute the actual time duration in ns. Relock timing is guaranteed by design and characterization. 4. The L2CR[L2SL] bit should be set for L2CLK frequencies less than 110 MHz. This adds more delay to each tap of the DLL. 5. Allowable skew between L2SYNC_OUT and L2SYNC_IN. 6. This output jitter number represents the maximum delay of one tap forward or one tap back from the current DLL tap as the phase comparator seeks to minimize the phase difference between L2SYNC_IN and the internal L2CLK. This number must be comprehended in the L2 timing analysis. The input jitter on SYSCLK affects L2CLK_OUT and the L2 address/data/control signals equally and, therefore, is already comprehended in the AC timing and does not have to be considered in the L2 timing analysis. 7. Guaranteed by design.
The L2CLK_OUT timing diagram is shown in Figure 7.
MPC755 RISC Microprocessor Hardware Specifications, Rev. 6.1 18 Freescale Semiconductor
Electrical and Thermal Characteristics L2 Single-Ended Clock Mode tCHCL L2CLK_OUTA VM tL2CR tL2CF
tL2CLK VM VM
L2CLK_OUTB
VM
VM
VM tL2CSKW
VM
L2SYNC_OUT
VM
VM
VM
VM
L2 Differential Clock Mode L2CLK_OUTB L2CLK_OUTA tCHCL VM
tL2CLK VM VM
L2SYNC_OUT
VM
VM
VM
VM = Midpoint Voltage (L2OVDD/2)
Figure 7. L2CLK_OUT Output Timing Diagram
4.2.4
L2 Bus AC Specifications
Table 12 provides the L2 bus interface AC timing specifications for the MPC755 as defined in Figure 8 and Figure 9 for the loading conditions described in Figure 10.
Table 12. L2 Bus Interface AC Timing Specifications
At recommended operating conditions (see Table 3)
All Speed Grades Parameter L2SYNC_IN rise and fall time Setup times: Data and parity Input hold times: Data and parity Valid times: All outputs when L2CR[14-15] = 00 All outputs when L2CR[14-15] = 01 All outputs when L2CR[14-15] = 10 All outputs when L2CR[14-15] = 11 Output hold times: All outputs when L2CR[14-15] = 00 All outputs when L2CR[14-15] = 01 All outputs when L2CR[14-15] = 10 All outputs when L2CR[14-15] = 11 tL2CHOX Symbol Min tL2CR, tL2CF tDVL2CH tDXL2CH tL2CHOV -- 1.2 0 -- -- -- -- 0.5 0.7 0.9 1.1 Max 1.0 -- -- 3.1 3.2 3.3 3.7 ns -- -- -- -- 3 ns ns ns ns 1 2 2 3, 4 Unit Notes
MPC755 RISC Microprocessor Hardware Specifications, Rev. 6.1 Freescale Semiconductor 19
Electrical and Thermal Characteristics
Table 12. L2 Bus Interface AC Timing Specifications (continued)
At recommended operating conditions (see Table 3)
All Speed Grades Parameter L2SYNC_IN to high impedance: All outputs when L2CR[14-15] = 00 All outputs when L2CR[14-15] = 01 All outputs when L2CR[14-15] = 10 All outputs when L2CR[14-15] = 11 Symbol Min tL2CHOZ -- -- -- -- Max ns 2.4 2.6 2.8 3.0 3, 5 Unit Notes
Notes: 1. Rise and fall times for the L2SYNC_IN input are measured from 20% to 80% of L2OVDD. 2. All input specifications are measured from the midpoint of the signal in question to the midpoint voltage of the rising edge of the input L2SYNC_IN (see Figure 8). Input timings are measured at the pins. 3. All output specifications are measured from the midpoint voltage of the rising edge of L2SYNC_IN to the midpoint of the signal in question. The output timings are measured at the pins. All output timings assume a purely resistive 50- load (see Figure 10). 4. The outputs are valid for both single-ended and differential L2CLK modes. For pipelined registered synchronous BurstRAMs, L2CR[14-15] = 01 or 10 is recommended. For pipelined late write synchronous BurstRAMs, L2CR[14-15] = 11 is recommended. 5. Guaranteed by design and characterization. 6. Revisions prior to Rev. 2.8 (Rev. E) were limited in performance and did not conform to this specification. For more information, refer to Section 10.2, "Part Numbers Not Fully Addressed by This Document."
MPC755 RISC Microprocessor Hardware Specifications, Rev. 6.1 20 Freescale Semiconductor
Electrical and Thermal Characteristics
Figure 8 shows the L2 bus input timing diagrams for the MPC755.
tL2CR L2SYNC_IN tDVL2CH L2 Data and Data Parity Inputs VM = Midpoint Voltage (L2OVDD/2) VM tDXL2CH tL2CF
Figure 8. L2 Bus Input Timing Diagrams
Figure 9 shows the L2 bus output timing diagrams for the MPC755.
L2SYNC_IN VM tL2CHOV VM tL2CHOX
All Outputs tL2CHOZ L2DATA BUS VM = Midpoint Voltage (L2OVDD/2)
Figure 9. L2 Bus Output Timing Diagrams
Figure 10 provides the AC test load for L2 interface of the MPC755.
Output Z0 = 50 L2OVDD/2
RL = 50
Figure 10. AC Test Load for the L2 Interface
4.2.5
IEEE 1149.1 AC Timing Specifications
Table 13. JTAG AC Timing Specifications (Independent of SYSCLK) 1
Table 13 provides the IEEE 1149.1 (JTAG) AC timing specifications as defined in Figure 12 through Figure 15.
At recommended operating conditions (see Table 3)
Parameter TCK frequency of operation TCK cycle time TCK clock pulse width measured at 1.4 V TCK rise and fall times
Symbol fTCLK tTCLK tJHJL tJR, tJF
Min 0 62.5 31 0
Max 16 -- -- 2
Unit MHz ns ns ns
Notes
MPC755 RISC Microprocessor Hardware Specifications, Rev. 6.1 Freescale Semiconductor 21
Electrical and Thermal Characteristics
Table 13. JTAG AC Timing Specifications (Independent of SYSCLK) 1 (continued)
At recommended operating conditions (see Table 3)
Parameter TRST assert time Input setup times:Boundary-scan data TMS, TDI Input hold times:Boundary-scan data TMS, TDI Valid times:Boundary-scan data TDO Output hold times:Boundary-scan data TDO TCK to output high impedance:Boundary-scan data TDO
Symbol tTRST tDVJH tIVJH tDXJH tIXJH tJLDV tJLOV tJLDH tJLOH tJLDZ tJLOZ
Min 25 4 0 15 12 -- -- 25 12 3 3
Max -- -- -- -- -- 4 4 -- -- 19 9
Unit ns ns ns ns ns ns
Notes 2 3 3 4 4 4, 5
Notes: 1. All outputs are measured from the midpoint voltage of the falling/rising edge of TCLK to the midpoint of the signal in question. The output timings are measured at the pins. All output timings assume a purely resistive 50- load (see Figure 11). Time-of-flight delays must be added for trace lengths, vias, and connectors in the system. 2. TRST is an asynchronous level sensitive signal which must be asserted for this minimum time to be recognized. 3. Non-JTAG signal input timing with respect to TCK. 4. Non-JTAG signal output timing with respect to TCK. 5. Guaranteed by design and characterization. Figure 11 provides
the AC test load for TDO and the boundary-scan outputs of the MPC755.
Output Z0 = 50 OVDD/2
RL = 50
Figure 11. AC Test Load for the JTAG Interface
Figure 12 provides the JTAG clock input timing diagram.
TCLK VM tJHJL tTCLK VM = Midpoint Voltage (OVDD/2) VM VM tJR tJF
Figure 12. JTAG Clock Input Timing Diagram
MPC755 RISC Microprocessor Hardware Specifications, Rev. 6.1 22 Freescale Semiconductor
Electrical and Thermal Characteristics
Figure 13 provides the TRST timing diagram.
TRST VM tTRST VM = Midpoint Voltage (OVDD/2) VM
Figure 13. TRST Timing Diagram
Figure 14 provides the boundary-scan timing diagram.
TCK VM tDVJH Boundary Data Inputs tJLDV Boundary Data Outputs tJLDH
Output Data Valid
VM
tDXJH
Input Data Valid
tJLDZ Boundary Data Outputs
Output Data Valid
VM = Midpoint Voltage (OVDD/2)
Figure 14. Boundary-Scan Timing Diagram
Figure 15 provides the test access port timing diagram.
TCK VM tIVJH TDI, TMS tJLOV tJLOH TDO tJLOZ TDO
Output Data Valid Output Data Valid Input Data Valid
VM
tIXJH
VM = Midpoint Voltage (OVDD/2)
Figure 15. Test Access Port Timing Diagram
MPC755 RISC Microprocessor Hardware Specifications, Rev. 6.1 Freescale Semiconductor 23
Pin Assignments
5
Part A
Pin Assignments
Figure 16 (in Part A) shows the pinout of the MPC745, 255 PBGA package as viewed from the top surface. Part B shows the side profile of the PBGA package to indicate the direction of the top surface view.
1 A B C D E F G H J K L M N P R T
Not to Scale
2
3
4
5
6
7
8
9
10
11 12 13
14 15 16
Part B
Substrate Assembly Encapsulant
View Die
Figure 16. Pinout of the MPC745, 255 PBGA Package as Viewed from the Top Surface
MPC755 RISC Microprocessor Hardware Specifications, Rev. 6.1 24 Freescale Semiconductor
Pin Assignments
Figure 17 (in Part A) shows the pinout of the MPC755, 360 PBGA and 360 CBGA packages as viewed from the top surface. Part B shows the side profile of the PBGA and CBGA package to indicate the direction of the top surface view.
Part A 1 A B C D E F G H J K L M N P R T U V W
Not to Scale
2
3
4
5
6
7
8
9
10
11 12 13
14 15 16
17 18 19
Part B
Substrate Assembly Encapsulant
View Die
Figure 17. Pinout of the MPC755, 360 PBGA and CBGA Packages as Viewed from the Top Surface
MPC755 RISC Microprocessor Hardware Specifications, Rev. 6.1 Freescale Semiconductor 25
Pinout Listings
6
Pinout Listings
Table 14. Pinout Listing for the MPC745, 255 PBGA Package
Signal Name A[0:31] Pin Number C16, E4, D13, F2, D14, G1, D15, E2, D16, D4, E13, G2, E15, H1, E16, H2, F13, J1, F14, J2, F15, H3, F16, F4, G13, K1, G15, K2, H16, M1, J15, P1 L2 K4 C1, B4, B3, B2 J4 A10 L1 B6 B1 E1 D8 A6 D7 J14 N1 H15 G4 P14, T16, R15, T15, R13, R12, P11, N11, R11, T12, T11, R10, P9, N9, T10, R9, T9, P8, N8, R8, T8, N7, R7, T7, P6, N6, R6, T6, R5, N5, T5, T4 K13, K15, K16, L16, L15, L13, L14, M16, M15, M13, N16, N15, N13, N14, P16, P15, R16, R14, T14, N10, P13, N12, T13, P3, N3, N4, R3, T1, T2, P4, T3, R4 M2, L3, N2, L4, R1, P2, M4, R2 G16 F1 C5, C12, E3, E6, E8, E9, E11, E14, F5, F7, F10, F12, G6, G8, G9, G11, H5, H7, H10, H12, J5, J7, J10, J12, K6, K8, K9, K11, L5, L7, L10, L12, M3, M6, M8, M9, M11, M14, P5, P12 A7 Active High I/O I/O I/F Voltage 1 OVDD Notes
Table 14 provides the pinout listing for the MPC745, 255 PBGA package.
AACK ABB AP[0:3] ARTRY AVDD BG BR BVSEL CI CKSTP_IN CKSTP_OUT CLK_OUT DBB DBG DBDIS DBWO DH[0:31]
Low Low High Low -- Low Low High Low Low Low -- Low Low Low Low High
Input I/O I/O I/O -- Input Output Input Output Input Output Output I/O Input Input Input I/O
OVDD OVDD OVDD OVDD 2.0 V OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD 3, 4, 5
DL[0:31]
High
I/O
OVDD
DP[0:7] DRTRY GBL GND
High Low Low --
I/O Input I/O --
OVDD OVDD OVDD GND
HRESET
Low
Input
OVDD
MPC755 RISC Microprocessor Hardware Specifications, Rev. 6.1 26 Freescale Semiconductor
Pinout Listings
Table 14. Pinout Listing for the MPC745, 255 PBGA Package (continued)
Signal Name INT L1_TSTCLK L2_TSTCLK LSSD_MODE MCP NC (No Connect) OVDD PLL_CFG[0:3] QACK QREQ RSRV SMI SRESET SYSCLK TA TBEN TBST TCK TDI TDO TEA TLBISYNC TMS TRST TS TSIZ[0:2] TT[0:4] WT VDD B15 D11 D12 B10 C13 B7, B8, C3, C6, C8, D5, D6, H4, J16, A4, A5, A2, A3, B5 C7, E5, E7, E10, E12, G3, G5, G12, G14, K3, K5, K12, K14, M5, M7, M10, M12, P7, P10 A8, B9, A9, D9 D3 J3 D1 A16 B14 C9 H14 C2 A14 C11 A11 A12 H13 C4 B11 C10 J13 A13, D10, B12 B13, A15, B16, C14, C15 D2 F6, F8, F9, F11, G7, G10, H6, H8, H9, H11, J6, J8, J9, J11, K7, K10, L6, L8, L9, L11 Pin Number Active Low High High Low Low -- -- High Low Low Low Low Low -- Low High Low High High High Low Low High Low Low High High Low -- I/O Input Input Input Input Input -- -- Input Input Output Output Input Input Input Input Input I/O Input Input Output Input Input Input Input I/O Output I/O Output -- I/F Voltage 1 OVDD -- -- -- OVDD -- 2.5 V/3.3 V OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD 2.0 V 5 5 5 2 2 2 Notes
MPC755 RISC Microprocessor Hardware Specifications, Rev. 6.1 Freescale Semiconductor 27
Pinout Listings
Table 14. Pinout Listing for the MPC745, 255 PBGA Package (continued)
Signal Name VOLTDET F3 Pin Number Active High I/O Output I/F Voltage 1 -- Notes 6
Notes: 1. OVDD supplies power to the processor bus, JTAG, and all control signals; and VDD supplies power to the processor core and the PLL (after filtering to become AVDD). These columns serve as a reference for the nominal voltage supported on a given signal as selected by the BVSEL pin configuration of Table 2 and the voltage supplied. For actual recommended value of Vin or supply voltages, see Table 3. 2. These are test signals for factory use only and must be pulled up to OVDD for normal machine operation. 3. This pin must be pulled up to OVDD for proper operation of the processor interface. To allow for future I/O voltage changes, provide the option to connect BVSEL independently to either OVDD or GND. 4. Uses 1 of 15 existing no connects in the MPC740, 255 BGA package. 5. Internal pull-up on die. 6. Internally tied to GND in the MPC745, 255 BGA package to indicate to the power supply that a low-voltage processor is present. This signal is not a power supply input. Caution: This differs from the MPC755, 360 BGA package.
Table 15 provides the pinout listing for the MPC755, 360 PBGA and CBGA packages.
Table 15. Pinout Listing for the MPC755, 360 BGA Package
Signal Name A[0:31] Pin Number A13, D2, H11, C1, B13, F2, C13, E5, D13, G7, F12, G3, G6, H2, E2, L3, G5, L4, G4, J4, H7, E1, G2, F3, J7, M3, H3, J2, J6, K3, K2, L2 N3 L7 C4, C5, C6, C7 L6 A8 H1 E7 W1 C2 B8 D7 E3 K5 G1 K1 D1 Active High I/O I/O I/F Voltage 1 OVDD Notes
AACK ABB AP[0:3] ARTRY AVDD BG BR BVSEL CI CKSTP_IN CKSTP_OUT CLK_OUT DBB DBDIS DBG DBWO
Low Low High Low -- Low Low High Low Low Low -- Low Low Low Low
Input I/O I/O I/O -- Input Output Input Output Input Output Output I/O Input Input Input
OVDD OVDD OVDD OVDD 2.0 V OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD 3, 5, 6
MPC755 RISC Microprocessor Hardware Specifications, Rev. 6.1 28 Freescale Semiconductor
Pinout Listings
Table 15. Pinout Listing for the MPC755, 360 BGA Package (continued)
Signal Name DH[0:31] Pin Number W12, W11, V11, T9, W10, U9, U10, M11, M9, P8, W7, P9, W9, R10, W6, V7, V6, U8, V9, T7, U7, R7, U6, W5, U5, W4, P7, V5, V4, W3, U4, R5 M6, P3, N4, N5, R3, M7, T2, N6, U2, N7, P11, V13, U12, P12, T13, W13, U13, V10, W8, T11, U11, V12, V8, T1, P1, V1, U1, N1, R2, V3, U3, W2 L1, P2, M2, V2, M1, N2, T3, R1 H6 B1 D10, D14, D16, D4, D6, E12, E8, F4, F6, F10, F14, F16, G9, G11, H5, H8, H10, H12, H15, J9, J11, K4, K6, K8, K10, K12, K14, K16, L9, L11, M5, M8, M10, M12, M15, N9, N11, P4, P6, P10, P14, P16, R8, R12, T4, T6, T10, T14, T16 B6 C11 F8 G18, H19, J13, J14, H17, H18, J16, J17, J18, J19, K15, K17, K18, M19, L19, L18, L17 L13 P17 N15 L16 U14, R13, W14, W15, V15, U15, W16, V16, W17, V17, U17, W18, V18, U18, V19, U19, T18, T17, R19, R18, R17, R15, P19, P18, P13, N14, N13, N19, N17, M17, M13, M18, H13, G19, G16, G15, G14, G13, F19, F18, F13, E19, E18, E17, E15, D19, D18, D17, C18, C17, B19, B18, B17, A18, A17, A16, B16, C16, A14, A15, C15, B14, C14, E13 V14, U16, T19, N18, H14, F17, C19, B15 D15, E14, E16, H16, J15, L15, M16, P15, R14, R16, T15, F15 L14 M14 F7 A19 N16 Active High I/O I/O I/F Voltage 1 OVDD Notes
DL[0:31]
High
I/O
OVDD
DP[0:7] DRTRY GBL GND
High Low Low --
I/O Input I/O --
OVDD OVDD OVDD GND
HRESET INT L1_TSTCLK L2ADDR[16:0] L2AVDD L2CE L2CLK_OUTA L2CLK_OUTB L2DATA[0:63]
Low Low High High -- Low -- -- High
Input Input Input Output -- Output Output Output I/O
OVDD OVDD -- L2OVDD 2.0 V L2OVDD L2OVDD L2OVDD L2OVDD 2
L2DP[0:7] L2OVDD L2SYNC_IN L2SYNC_OUT L2_TSTCLK L2VSEL L2WE
High -- -- -- High High Low
I/O -- Input Output Input Input Output
L2OVDD L2OVDD L2OVDD L2OVDD -- L2OVDD L2OVDD 2 1, 5, 6, 7
MPC755 RISC Microprocessor Hardware Specifications, Rev. 6.1 Freescale Semiconductor 29
Pinout Listings
Table 15. Pinout Listing for the MPC755, 360 BGA Package (continued)
Signal Name L2ZZ LSSD_MODE MCP NC (No Connect) OVDD PLL_CFG[0:3] QACK QREQ RSRV SMI SRESET SYSCLK TA TBEN TBST TCK TDI TDO TEA TLBISYNC TMS TRST TS TSIZ[0:2] TT[0:4] WT VDD G17 F9 B11 B3, B4, B5, W19, K9, K11 4, K19 4 D5, D8, D12, E4, E6, E9, E11, F5, H4, J5, L5, M4, P5, R4, R6, R9, R11, T5, T8, T12 A4, A5, A6, A7 B2 J3 D3 A12 E10 H9 F1 A2 A11 B10 B7 D9 J1 A3 C8 A10 K7 A9, B9, C9 C10, D11, B12, C12, F11 C3 G8, G10, G12, J8, J10, J12, L8, L10, L12, N8, N10, N12 Pin Number Active High Low Low -- -- High Low Low Low Low Low -- Low High Low High High High Low Low High Low Low High High Low -- I/O Output Input Input -- -- Input Input Output Output Input Input Input Input Input I/O Input Input Output Input Input Input Input I/O Output I/O Output -- I/F Voltage 1 L2OVDD -- OVDD -- OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVdd OVDD OVDD OVDD OVDD OVDD OVDD OVDD OVDD 2.0 V 6 6 6 2 Notes
MPC755 RISC Microprocessor Hardware Specifications, Rev. 6.1 30 Freescale Semiconductor
Package Description
Table 15. Pinout Listing for the MPC755, 360 BGA Package (continued)
Signal Name VOLTDET K13 Pin Number Active High I/O Output I/F Voltage 1 L2OVDD Notes 8
Notes: 1. OVDD supplies power to the processor bus, JTAG, and all control signals except the L2 cache controls (L2CE, L2WE, and L2ZZ); L2OVDD supplies power to the L2 cache interface (L2ADDR[0:16], L2DATA[0:63], L2DP[0:7], and L2SYNC_OUT) and the L2 control signals; and VDD supplies power to the processor core and the PLL and DLL (after filtering to become AVDD and L2AVDD, respectively). These columns serve as a reference for the nominal voltage supported on a given signal as selected by the BVSEL/L2VSEL pin configurations of Table 2 and the voltage supplied. For actual recommended value of Vin or supply voltages, see Table 3. 2. These are test signals for factory use only and must be pulled up to OVDD for normal machine operation. 3. This pin must be pulled up to OVDD for proper operation of the processor interface. To allow for future I/O voltage changes, provide the option to connect BVSEL independently to either OVDD or GND. 4. These pins are reserved for potential future use as additional L2 address pins. 5. Uses one of nine existing no connects in the MPC750, 360 BGA package. 6. Internal pull-up on die. 7. This pin must be pulled up to L2OVDD for proper operation of the processor interface. To allow for future I/O voltage changes, provide the option to connect L2VSEL independently to either L2OVDD or GND. 8. Internally tied to L2OVDD in the MPC755, 360 BGA package to indicate the power present at the L2 cache interface. This signal is not a power supply input. Caution: This differs from the MPC745, 255 BGA package.
7
Package Description
The following sections provide the package parameters and mechanical dimensions for the MPC745, 255 PBGA package, as well as the MPC755, 360 CBGA and PBGA packages. While both the MPC755 plastic and ceramic packages are described here, both packages are not guaranteed to be available at the same time. All new designs should allow for either ceramic or plastic BGA packages for this device. For more information on designing a common footprint for both plastic and ceramic package types, see the Freescale Flip-Chip Plastic Ball Grid Array Presentation. The MPC755 was initially sampled in a CBGA package, but production units are currently provided in both a CBGA and a PBGA package. Because of the better long-term device-to-board interconnect reliability of the PBGA package, Freescale recommends use of a PBGA package except where circumstances dictate use of a CBGA package.
7.1
Package Parameters for the MPC745 PBGA
Package outline Interconnects Pitch Minimum module height Maximum module height Ball diameter (typical) 21 x 21 mm 255 (16 x 16 ball array - 1) 1.27 mm (50 mil) 2.25 mm 2.80 mm 0.75 mm (29.5 mil)
The package parameters are as provided in the following list. The package type is 21 x 21 mm, 255-lead plastic ball grid array (PBGA).
MPC755 RISC Microprocessor Hardware Specifications, Rev. 6.1 Freescale Semiconductor 31
Package Description
7.2
Mechanical Dimensions for the MPC745 PBGA
Figure 18 provides the mechanical dimensions and bottom surface nomenclature for the MPC745, 255 PBGA package.
0.2 D
A1 CORNER
A
D1 1 C 0.2 C
E E1
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. TOP SIDE A1 CORNER INDEX IS A METALIZED FEATURE WITH VARIOUS SHAPES. BOTTOM SIDE A1 CORNER IS DESIGNATED WITH A BALL MISSING FROM THE ARRAY. 4. CAPACITOR PADS MAY BE UNPOPULATED.
2X
0.2 B
Millimeters
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 T R P N M L K J H G F E D C B A
DIM A A1 A2 A3 b
A3 A2 A1 A
Min 2.25 0.50 1.00 -- 0.60 6.75
Max 2.80 0.70 1.20 0.60 0.90
D D1 E E1 e
21.00 BSC 21.00 BSC 7.87 1.27 BSC
e
255X
b 0.3 C A B 0.15 C
Figure 18. Mechanical Dimensions and Bottom Surface Nomenclature for the MPC745, 255 PBGA Package
MPC755 RISC Microprocessor Hardware Specifications, Rev. 6.1 32 Freescale Semiconductor
Package Description
7.3
Package Parameters for the MPC755 CBGA
Package outline Interconnects Pitch Minimum module height Maximum module height Ball diameter 25 x 25 mm 360 (19 x 19 ball array - 1) 1.27 mm (50 mil) 2.65 mm 3.20 mm 0.89 mm (35 mil)
The package parameters are as provided in the following list. The package type is 25 x 25 mm, 360-lead ceramic ball grid array (CBGA).
MPC755 RISC Microprocessor Hardware Specifications, Rev. 6.1 Freescale Semiconductor 33
Package Description
7.4
Mechanical Dimensions for the MPC755 CBGA
Figure 19 provides the mechanical dimensions and bottom surface nomenclature for the MPC755, 360 CBGA package.
2X
0.2 D
A1 CORNER
A C
D1 1 0.2 C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. TOP SIDE A1 CORNER INDEX IS A METALIZED FEATURE WITH VARIOUS SHAPES. BOTTOM SIDE A1 CORNER IS DESIGNATED WITH A BALL MISSING FROM THE ARRAY. E1
E
2X
0.2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 W V U T R P N M L K J H G F E D C B A
Millimeters DIM A A1 A2 A3 b
A3 A2 A1 A
Min 2.65 0.79 1.10 -- 0.82 6.75
Max 3.20 0.99 1.30 0.60 0.93
D D1 E E1 e
25.00 BSC 25.00 BSC 7.87 1.27 BSC
e
360X
0.3 C A B b 0.15 C
Figure 19. Mechanical Dimensions and Bottom Surface Nomenclature for the MPC755, 360 CBGA Package
MPC755 RISC Microprocessor Hardware Specifications, Rev. 6.1 34 Freescale Semiconductor
Package Description
7.5
Package Parameters for the MPC755 PBGA
Package outline Interconnects Pitch Minimum module height Maximum module height Ball diameter 25 x 25 mm 360 (19 x 19 ball array - 1) 1.27 mm (50 mil) 2.22 mm 2.77 mm 0.75 mm (29.5 mil)
The package parameters are as provided in the following list. The package type is 25 x 25 mm, 360-lead plastic ball grid array (PBGA).
MPC755 RISC Microprocessor Hardware Specifications, Rev. 6.1 Freescale Semiconductor 35
System Design Information
7.6
Mechanical Dimensions for the MPC755
Figure 20 provides the mechanical dimensions and bottom surface nomenclature for the MPC755, 360 PBGA package.
2X
0.2 D
A1 CORNER
A C 0.2 C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. TOP SIDE A1 CORNER INDEX IS A METALIZED FEATURE WITH VARIOUS SHAPES. BOTTOM SIDE A1 CORNER IS DESIGNATED WITH A BALL MISSING FROM THE ARRAY.
D1 1 E1
E
2X
0.2 B
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 W V U T R P N M L K J H G F E D C B A
Millimeters DIM A A1 A2 A3 b
A3 A2 A1 A
Min 2.22 0.50 1.00 -- 0.60 6.75
Max 2.77 0.70 1.20 0.60 0.90
D D1 E E1 e
25.00 BSC 25.00 BSC 7.87 1.27 BSC
e
360X
b
0.3 C A B 0.15 C
Figure 20. Mechanical Dimensions and Bottom Surface Nomenclature for the MPC755, 360 PBGA Package
8
8.1
System Design Information
PLL Configuration
This section provides electrical and thermal design recommendations for successful application of the MPC755.
The MPC755 PLL is configured by the PLL_CFG[0:3] signals. For a given SYSCLK (bus) frequency, the PLL configuration signals set the internal CPU and VCO frequency of operation. These must be chosen such that they comply with Table 8. Table 16 shows the valid configurations of these signals and an example illustrating the core and VCO frequencies resulting from various PLL configurations and example bus frequencies. In this example,
MPC755 RISC Microprocessor Hardware Specifications, Rev. 6.1 36 Freescale Semiconductor
System Design Information
shaded cells represent settings that, for a given SYSCLK frequency, result in core and/or VCO frequencies that do not comply with the 400-MHz column in Table 8.
Table 16. MPC755 Microprocessor PLL Configuration Example for 400 MHz Parts
Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz) PLL_CFG [0:3] Bus-toCore Multiplier 2x 3x 3.5x 4x 4.5x 5x 5.5x 6x 6.5x 7x 7.5x 8x 10x Core-toVCO Multiplier 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x 2x Bus 33 MHz -- -- -- -- -- -- -- 200 (400) 216 (433) 233 (466) 250 (500) 266 (533) 333 (666) Bus 50 MHz -- -- -- 200 (400) 225 (450) 250 (500) 275 (550) 300 (600) 325 (650) 350 (700) 375 (750) 400 (800) -- Bus 66 MHz -- 200 (400) 233 (466) 266 (533) 300 (600) 333 (666) 366 (733) 400 (800) -- -- -- -- -- Bus 75 MHz -- 225 (450) 263 (525) 300 (600) 338 (675) 375 (750) -- -- -- -- -- -- -- Bus 80 MHz -- 240 (480) 280 (560) 320 (640) 360 (720) 400 (800) -- -- -- -- -- -- -- Bus 100 MHz 200 (400) 300 (600) 350 (700) 400 (800) -- -- -- -- -- -- -- -- --
0100 1000 1110 1010 0111 1011 1001 1101 0101 0010 0001 1100 0110 0011 1111
PLL off/bypass PLL off
PLL off, SYSCLK clocks core circuitry directly, 1x bus-to-core implied PLL off, no core clocking occurs
Notes: 1. PLL_CFG[0:3] settings not listed are reserved. 2. The sample bus-to-core frequencies shown are for reference only. Some PLL configurations may select bus, core, or VCO frequencies which are not useful, not supported, or not tested for by the MPC755; see Section 4.2.1, "Clock AC Specifications," for valid SYSCLK, core, and VCO frequencies. 3. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is disabled, and the bus mode is set for 1:1 mode operation. This mode is intended for factory use and emulator tool use only. Note: The AC timing specifications given in this document do not apply in PLL-bypass mode. 4. In PLL off mode, no clocking occurs inside the MPC755 regardless of the SYSCLK input.
MPC755 RISC Microprocessor Hardware Specifications, Rev. 6.1 Freescale Semiconductor 37
System Design Information
The MPC755 generates the clock for the external L2 synchronous data SRAMs by dividing the core clock frequency of the MPC755. The divided-down clock is then phase-adjusted by an on-chip delay-lock-loop (DLL) circuit and should be routed from the MPC755 to the external RAMs. A separate clock output, L2SYNC_OUT is sent out half the distance to the SRAMs and then returned as an input to the DLL on pin L2SYNC_IN so that the rising-edge of the clock as seen at the external RAMs can be aligned to the clocking of the internal latches in the L2 bus interface. The core-to-L2 frequency divisor for the L2 PLL is selected through the L2CLK bits of the L2CR register. Generally, the divisor must be chosen according to the frequency supported by the external RAMs, the frequency of the MPC755 core, and the phase adjustment range that the L2 DLL supports. Table 17 shows various example L2 clock frequencies that can be obtained for a given set of core frequencies. The minimum L2 frequency target is 80 MHz.
Table 17. Sample Core-to-L2 Frequencies
Core Frequency (MHz) 250 266 275 300 325 333 350 366 375 400 /1 250 266 275 300 325 333 350 366 375 400 /1.5 166 177 183 200 217 222 233 244 250 266 /2 125 133 138 150 163 167 175 183 188 200 /2.5 100 106 110 120 130 133 140 146 150 160 /3 83 89 92 100 108 111 117 122 125 133
Note: The core and L2 frequencies are for reference only. Some examples may represent core or L2 frequencies which are not useful, not supported, or not tested for by the MPC755; see Section 4.2.3, "L2 Clock AC Specifications," for valid L2CLK frequencies. The L2CR[L2SL] bit should be set for L2CLK frequencies less than 110 MHz.
8.2
PLL Power Supply Filtering
The AVDD and L2AVDD power signals are provided on the MPC755 to provide power to the clock generation PLL and L2 cache DLL, respectively. To ensure stability of the internal clock, the power supplied to the AVDD input signal should be filtered of any noise in the 500 kHz to 10 MHz resonant frequency range of the PLL. A circuit similar to the one shown in Figure 21 using surface mount capacitors with minimum Effective Series Inductance (ESL) is recommended. Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a single large value capacitor. The circuit should be placed as close as possible to the AVDD pin to minimize noise coupled from nearby circuits. An identical but separate circuit should be placed as close as possible to the L2AVDD pin. It is often possible to route directly from the capacitors to the AVDD pin, which is on the periphery of the 360 BGA footprint, without the inductance of vias. The L2AVDD pin may be more difficult to route, but is proportionately less critical.
MPC755 RISC Microprocessor Hardware Specifications, Rev. 6.1 38 Freescale Semiconductor
System Design Information
Figure 21 shows the PLL power supply filter circuit.
VDD 10 2.2 F 2.2 F Low ESL Surface Mount Capacitors GND AVDD (or L2AVDD)
Figure 21. PLL Power Supply Filter Circuit
8.3
Decoupling Recommendations
Due to the MPC755 dynamic power management feature, large address and data buses, and high operating frequencies, the MPC755 can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads. This noise must be prevented from reaching other components in the MPC755 system, and the MPC755 itself requires a clean, tightly regulated source of power. Therefore, it is recommended that the system designer place at least one decoupling capacitor at each VDD, OVDD, and L2OVDD pin of the MPC755. It is also recommended that these decoupling capacitors receive their power from separate VDD, (L2)OVDD, and GND power planes in the PCB, utilizing short traces to minimize inductance. These capacitors should have a value of 0.01 or 0.1 F. Only ceramic SMT (surface mount technology) capacitors should be used to minimize lead inductance, preferably 0508 or 0603 orientations where connections are made along the length of the part. In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB, feeding the VDD, L2OVDD, and OVDD planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors should have a low ESR (equivalent series resistance) rating to ensure the quick response time necessary. They should also be connected to the power and ground planes through two vias to minimize inductance. Suggested bulk capacitors:100-330 F (AVX TPS tantalum or Sanyo OSCON).
8.4
Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level through a resistor. Unused active low inputs should be tied to OVDD. Unused active high inputs should be connected to GND. All NC (no connect) signals must remain unconnected. Power and ground connections must be made to all external VDD, OVDD, L2OVDD, and GND pins of the MPC755. Note that power must be supplied to L2OVDD even if the L2 interface of the MPC755 will not be used; it is recommended to connect L2OVDD to OVDD and L2VSEL to BVSEL if the L2 interface is unused. (This requirement does not apply to the MPC745 since it has neither an L2 interface nor L2OVDD pins.)
8.5
Output Buffer DC Impedance
The MPC755 60x and L2 I/O drivers are characterized over process, voltage, and temperature. To measure Z0, an external resistor is connected from the chip pad to (L2)OVDD or GND. Then, the value of each resistor is varied until the pad voltage is (L2)OVDD/2 (see Figure 22). The output impedance is the average of two components, the resistances of the pull-up and pull-down devices. When data is held low, SW2 is closed (SW1 is open), and RN is trimmed until the voltage at the pad equals (L2)OVDD/2.
MPC755 RISC Microprocessor Hardware Specifications, Rev. 6.1 Freescale Semiconductor 39
System Design Information
RN then becomes the resistance of the pull-down devices. When data is held high, SW1 is closed (SW2 is open), and RP is trimmed until the voltage at the pad equals (L2)OVDD/2. RP then becomes the resistance of the pull-up devices. Figure 22 describes the driver impedance measurement circuit described above.
(L2)OVDD (L2)OVDD
RN SW2 Data Pad SW1
RP
OGND
Figure 22. Driver Impedance Measurement Circuit
Alternately, the following is another method to determine the output impedance of the MPC755. A voltage source, Vforce, is connected to the output of the MPC755 as shown in Figure 23. Data is held low, the voltage source is set to a value that is equal to (L2)OVDD/2 and the current sourced by Vforce is measured. The voltage drop across the pull-down device, which is equal to (L2)OVDD/2, is divided by the measured current to determine the output impedance of the pull-down device, RN. Similarly, the impedance of the pull-up device is determined by dividing the voltage drop of the pull-up, (L2)OVDD/2, by the current sank by the pull-up when the data is high and Vforce is equal to (L2)OVDD/2. This method can be employed with either empirical data from a test setup or with data from simulation models, such as IBIS. RP and RN are designed to be close to each other in value. Then Z0 = (RP + RN)/2.
MPC755 RISC Microprocessor Hardware Specifications, Rev. 6.1 40 Freescale Semiconductor
System Design Information
Figure 23 describes the alternate driver impedance measurement circuit.
(L2)OVDD
Data
BGA Pin
Vforce
OGND
Figure 23. Alternate Driver Impedance Measurement Circuit
Table 18 summarizes the signal impedance results. The driver impedance values were characterized at 0, 65, and 105C. The impedance increases with junction temperature and is relatively unaffected by bus voltage.
Table 18. Impedance Characteristics
VDD = 2.0 V, OVDD = 3.3 V, Tj = 0-105C
Impedance RN RP
Processor Bus 25-36 26-39
L2 Bus 25-36 26-39
Symbol Z0 Z0
Unit
8.6
Pull-Up Resistor Requirements
The MPC755 requires pull-up resistors (1-5 k) on several control pins of the bus interface to maintain the control signals in the negated state after they have been actively negated and released by the MPC755 or other bus masters. These pins are TS, ABB, AACK, ARTRY, DBB, DBWO, TA, TEA, and DBDIS. DRTRY should also be connected to a pull-up resistor (1-5 k) if it will be used by the system; otherwise, this signal should be connected to HRESET to select NO-DRTRY mode (see the MPC750 RISC Microprocessor Family User's Manual for more information on this mode). Three test pins also require pull-up resistors (100 -1 k). These pins are L1_TSTCLK, L2_TSTCLK, and LSSD_MODE. These signals are for factory use only and must be pulled up to OVDD for normal machine operation. In addition, CKSTP_OUT is an open-drain style output that requires a pull-up resistor (1-5 k) if it is used by the system. During inactive periods on the bus, the address and transfer attributes may not be driven by any master and may, therefore, float in the high-impedance state for relatively long periods of time. Since the MPC755 must continually monitor these signals for snooping, this float condition may cause additional power draw by the input receivers on the MPC755 or by other receivers in the system. These signals can be pulled up through weak (10-k) pull-up resistors by the system or may be otherwise driven by the system during inactive periods of the bus to avoid this
MPC755 RISC Microprocessor Hardware Specifications, Rev. 6.1 Freescale Semiconductor 41
System Design Information
additional power draw, but address bus pull-up resistors are not neccessary for proper device operation. The snooped address and transfer attribute inputs are: A[0:31], AP[0:3], TT[0:4], TBST, and GBL. The data bus input receivers are normally turned off when no read operation is in progress and, therefore, do not require pull-up resistors on the bus. Other data bus receivers in the system, however, may require pull-ups, or that those signals be otherwise driven by the system during inactive periods by the system. The data bus signals are: DH[0:31], DL[0:31], and DP[0:7]. If 32-bit data bus mode is selected, the input receivers of the unused data and parity bits will be disabled, and their outputs will drive logic zeros when they would otherwise normally be driven. For this mode, these pins do not require pull-up resistors, and should be left unconnected by the system to minimize possible output switching. If address or data parity is not used by the system, and the respective parity checking is disabled through HID0, the input receivers for those pins are disabled, and those pins do not require pull-up resistors and should be left unconnected by the system. If all parity generation is disabled through HID0, then all parity checking should also be disabled through HID0, and all parity pins may be left unconnected by the system. The L2 interface does not require pull-up resistors.
8.7
JTAG Configuration Signals
Boundary scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the IEEE 1149.1 specification, but is provided on all processors that implement the PowerPC architecture. While it is possible to force the TAP controller to the reset state using only the TCK and TMS signals, more reliable power-on reset performance will be obtained if the TRST signal is asserted during power-on reset. Because the JTAG interface is also used for accessing the common on-chip processor (COP) function, simply tying TRST to HRESET is not practical. The COP function of these processors allows a remote computer system (typically, a PC with dedicated hardware and debugging software) to access and control the internal operations of the processor. The COP interface connects primarily through the JTAG port of the processor, with some additional status monitoring signals. The COP port requires the ability to independently assert HRESET or TRST in order to fully control the processor. If the target system has independent reset sources, such as voltage monitors, watchdog timers, power supply failures, or push-button switches, then the COP reset signals must be merged into these signals with logic. The arrangement shown in Figure 24 allows the COP port to independently assert HRESET or TRST, while ensuring that the target can drive HRESET as well. If the JTAG interface and COP header will not be used, TRST should be tied to HRESET through a 0- isolation resistor so that it is asserted when the system reset signal (HRESET) is asserted ensuring that the JTAG scan chain is initialized during power-on. While Freescale recommends that the COP header be designed into the system as shown in Figure 24, if this is not possible, the isolation resistor will allow future access to TRST in the case where a JTAG interface may need to be wired onto the system in debug situations. The COP header shown in Figure 24 adds many benefits--breakpoints, watchpoints, register and memory examination/modification, and other standard debugger features are possible through this interface--and can be as inexpensive as an unpopulated footprint for a header to be added when needed. The COP interface has a standard header for connection to the target system, based on the 0.025" square-post 0.100" centered header assembly (often called a Berg header). The connector typically has pin 14 removed as a connector key.
MPC755 RISC Microprocessor Hardware Specifications, Rev. 6.1 42 Freescale Semiconductor
System Design Information
From Target Board Sources (if any)
SRESET HRESET QACK 13 11 HRESET SRESET 10 k 10 k 10 k 10 k 05
SRESET HRESET
OVDD OVDD OVDD OVDD
1 3 5 7 9 11
2 4 6 8 10 12
4 6 51 15 Key 14 2 8 COP Header 9 1 3 7 2 10 12 16
TRST VDD_SENSE 2 k CHKSTP_OUT 10 k 10 k CHKSTP_IN TMS TDO TDI TCK QACK NC NC 2 k 3 10 k 4 10 k
TRST OVDD OVDD CHKSTP_OUT OVDD OVDD CHKSTP_IN TMS TDO TDI TCK QACK OVDD
KEY 13 No pin
15
16
COP Connector Physical Pin Out
Notes: 1. RUN/STOP, normally found on pin 5 of the COP header, is not implemented on the MPC755. Connect pin 5 of the COP header to OVDD with a 10-k pull-up resistor. 2. Key location; pin 14 is not physically present on the COP header. 3. Component not populated. Populate only if debug tool does not drive QACK. 4. Populate only if debug tool uses an open-drain type output and does not actively deassert QACK. 5. If the JTAG interface is implemented, connect HRESET from the target source to TRST from the COP header though an AND gate to TRST of the part. If the JTAG interface is not implemented, connect HRESET from the target source to TRST of the part through a 0- isolation reisistor.
Figure 24. JTAG Interface Connection
There is no standardized way to number the COP header shown in Figure 24; consequently, many different pin numbers have been observed from emulator vendors. Some are numbered top-to-bottom then left-to-right, while
MPC755 RISC Microprocessor Hardware Specifications, Rev. 6.1 Freescale Semiconductor 43
System Design Information
others use left-to-right then top-to-bottom, while still others number the pins counter clockwise from pin 1 (as with an IC). Regardless of the numbering, the signal placement recommended in Figure 25 is common to all known emulators. The QACK signal shown in Figure 24 is usually connected to the PCI bridge chip in a system and is an input to the MPC755 informing it that it can go into the quiescent state. Under normal operation this occurs during a low-power mode selection. In order for COP to work, the MPC755 must see this signal asserted (pulled down). While shown on the COP header, not all emulator products drive this signal. If the product does not, a pull-down resistor can be populated to assert this signal. Additionally, some emulator products implement open-drain type outputs and can only drive QACK asserted; for these tools, a pull-up resistor can be implemented to ensure this signal is deasserted when it is not being driven by the tool. Note that the pull-up and pull-down resistors on the QACK signal are mutually exclusive and it is never necessary to populate both in a system. To preserve correct power-down operation, QACK should be merged via logic so that it also can be driven by the PCI bridge.
8.8
Thermal Management Information
This section provides thermal management information for the ceramic ball grid array (CBGA) package for air-cooled applications. Proper thermal control design is primarily dependent on the system-level design--the heat sink, airflow, and thermal interface material. To reduce the die-junction temperature, heat sinks may be attached to the package by several methods--adhesive, spring clip to holes in the printed-circuit board or package, and mounting clip and screw assembly; see Figure 25. This spring force should not exceed 5.5 pounds of force. Figure 25 describes the package exploded cross-sectional view with several heat sink options.
Heat Sink Heat Sink Clip Adhesive or Thermal Interface Material CBGA Package
Printed-Circuit Board
Option
Figure 25. Package Exploded Cross-Sectional View with Several Heat Sink Options
The board designer can choose between several types of heat sinks to place on the MPC755. There are several commercially-available heat sinks for the MPC755 provided by the following vendors: Aavid Thermalloy 80 Commercial St. Concord, NH 03301 Internet: www.aavidthermalloy.com 603-224-9988
MPC755 RISC Microprocessor Hardware Specifications, Rev. 6.1 44 Freescale Semiconductor
System Design Information
Alpha Novatech 473 Sapena Ct. #15 Santa Clara, CA 95054 Internet: www.alphanovatech.com International Electronic Research Corporation (IERC) 413 North Moss St. Burbank, CA 91502 Internet: www.ctscorp.com Tyco Electronics Chip CoolersTM P.O. Box 3668 Harrisburg, PA 17105-3668 Internet: www.chipcoolers.com Wakefield Engineering 33 Bridge St. Pelham, NH 03076 Internet: www.wakefield.com
408-749-7601
818-842-7277
800-522-6752
603-635-5102
Ultimately, the final selection of an appropriate heat sink depends on many factors, such as thermal performance at a given air velocity, spatial volume, mass, attachment method, assembly, and cost.
8.8.1
Internal Package Conduction Resistance
For the exposed-die packaging technology, shown in Table 4, the intrinsic conduction thermal resistance paths are as follows: * * The die junction-to-case (or top-of-die for exposed silicon) thermal resistance The die junction-to-ball thermal resistance
Figure 26 depicts the primary heat transfer path for a package with an attached heat sink mounted to a printed-circuit board. Heat generated on the active side of the chip is conducted through the silicon, then through the heat sink attach material (or thermal interface material), and finally to the heat sink where it is removed by forced-air convection. Since the silicon thermal resistance is quite small, for a first-order analysis, the temperature drop in the silicon may be neglected. Thus, the heat sink attach material and the heat sink conduction/convective thermal resistances are the dominant terms.
MPC755 RISC Microprocessor Hardware Specifications, Rev. 6.1 Freescale Semiconductor 45
System Design Information External Resistance Radiation Convection
Heat Sink Thermal Interface Material Internal Resistance Die/Package Die Junction Package/Leads Printed-Circuit Board
External Resistance
Radiation
Convection
(Note the internal versus external package resistance.)
Figure 26. C4 Package with Heat Sink Mounted to a Printed-Circuit Board
8.8.2
Adhesives and Thermal Interface Materials
A thermal interface material is recommended at the package lid-to-heat sink interface to minimize the thermal contact resistance. For those applications where the heat sink is attached by spring clip mechanism, Figure 27 shows the thermal performance of three thin-sheet thermal-interface materials (silicone, graphite/oil, floroether oil), a bare joint, and a joint with thermal grease as a function of contact pressure. As shown, the performance of these thermal interface materials improves with increasing contact pressure. The use of thermal grease significantly reduces the interface thermal resistance. That is, the bare joint results in a thermal resistance approximately seven times greater than the thermal grease joint. Heat sinks are attached to the package by means of a spring clip to holes in the printed-circuit board (see Figure 25). This spring force should not exceed 5.5 pounds of force. Therefore, the synthetic grease offers the best thermal performance, considering the low interface pressure. Of course, the selection of any thermal interface material depends on many factors--thermal performance requirements, manufacturability, service temperature, dielectric properties, cost, etc.
MPC755 RISC Microprocessor Hardware Specifications, Rev. 6.1 46 Freescale Semiconductor
System Design Information
Figure 27 describes the thermal performance of select thermal interface materials.
2
Silicone Sheet (0.006 in.) Bare Joint Floroether Oil Sheet (0.007 in.) Graphite/Oil Sheet (0.005 in.) Synthetic Grease
1.5 Specific Thermal Resistance (K-in.2/W)
1
0.5
0 0 10 20 30 40 50 60 70 80 Contact Pressure (psi)
Figure 27. Thermal Performance of Select Thermal Interface Materials
The board designer can choose between several types of thermal interface. Heat sink adhesive materials should be selected based on high conductivity, yet adequate mechanical strength to meet equipment shock/vibration requirements. There are several commercially-available thermal interfaces and adhesive materials provided by the following vendors: The Bergquist Company 18930 West 78th St. Chanhassen, MN 55317 Internet: www.bergquistcompany.com Chomerics, Inc. 77 Dragon Ct. Woburn, MA 01888-4014 Internet: www.chomerics.com Dow-Corning Corporation Dow-Corning Electronic Materials 2200 W. Salzburg Rd. Midland, MI 48686-0997 Internet: www.dow.com 800-347-4572
781-935-4850
800-248-2481
MPC755 RISC Microprocessor Hardware Specifications, Rev. 6.1 Freescale Semiconductor 47
System Design Information
Shin-Etsu MicroSi, Inc. 10028 S. 51st St. Phoenix, AZ 85044 Internet: www.microsi.com Thermagon Inc. 4707 Detroit Ave. Cleveland, OH 44102 Internet: www.thermagon.com
888-642-7674
888-246-9050
8.8.3
Heat Sink Selection Example
Tj = Ta + Tr + (jc + int + sa) x Pd
This section provides a heat sink selection example using one of the commercially-available heat sinks. For preliminary heat sink sizing, the die-junction temperature can be expressed as follows: where: Tj is the die-junction temperature Ta is the inlet cabinet ambient temperature Tr is the air temperature rise within the computer cabinet jc is the junction-to-case thermal resistance int is the adhesive or interface material thermal resistance sa is the heat sink base-to-ambient thermal resistance Pd is the power dissipated by the device During operation the die-junction temperatures (Tj) should be maintained less than the value specified in Table 3. The temperature of air cooling the component greatly depends on the ambient inlet air temperature and the air temperature rise within the electronic cabinet. An electronic cabinet inlet-air temperature (Ta) may range from 30 to 40C. The air temperature rise within a cabinet (Tr) may be in the range of 5 to 10C. The thermal resistance of the thermal interface material (int) is typically about 1C/W. Assuming a Ta of 30C, a Tr of 5C, a CBGA package Rjc < 0.1, and a power consumption (Pd) of 5.0 W, the following expression for Tj is obtained: Die-junction temperature: Tj = 30C + 5C + (0.1C/W + 1.0C/W + sa) x 5.0 W For a Thermalloy heat sink #2328B, the heat sink-to-ambient thermal resistance (sa) versus airflow velocity is shown in Figure 28. Assuming an air velocity of 0.5 m/s, we have an effective Rsa of 7C/W, thus Tj = 30C + 5C + (0.1C/W + 1.0C/W + 7C/W) x 5.0 W, resulting in a die-junction temperature of approximately 76C which is well within the maximum operating temperature of the component. Other heat sinks offered by Aavid Thermalloy, Alpha Novatech, The Bergquist Company, IERC, Chip Coolers, and Wakefield Engineering offer different heat sink-to-ambient thermal resistances, and may or may not need airflow.
MPC755 RISC Microprocessor Hardware Specifications, Rev. 6.1 48 Freescale Semiconductor
System Design Information 8
Thermalloy #2328B Pin-Fin Heat Sink (25 x 28 x 15 mm)
7
6 Heat Sink Thermal Resistance (C/W)
5
4
3
2
1 0 0.5 1 1.5 2 2.5 3 3.5 Approach Air Velocity (m/s)
Figure 28. Thermalloy #2328B Heat Sink-to-Ambient Thermal Resistance Versus Airflow Velocity
Though the die junction-to-ambient and the heat sink-to-ambient thermal resistances are a common figure-of-merit used for comparing the thermal performance of various microelectronic packaging technologies, one should exercise caution when only using this metric in determining thermal management because no single parameter can adequately describe three-dimensional heat flow. The final die-junction operating temperature, is not only a function of the component-level thermal resistance, but the system-level design and its operating conditions. In addition to the component's power consumption, a number of factors affect the final operating die-junction temperature--airflow, board population (local heat flux of adjacent components), heat sink efficiency, heat sink attach, heat sink placement, next-level interconnect technology, system air temperature rise, altitude, etc. Due to the complexity and the many variations of system-level boundary conditions for today's microelectronic equipment, the combined effects of the heat transfer mechanisms (radiation, convection, and conduction) may vary widely. For these reasons, we recommend using conjugate heat transfer models for the board, as well as, system-level designs.
MPC755 RISC Microprocessor Hardware Specifications, Rev. 6.1 Freescale Semiconductor 49
Document Revision History
9
Document Revision History
Table 19. Document Revision History
Rev. No. 0 1 Substantive Change(s) Product announced. Documentation made publicly available. Corrected errors in Section 1.2. Removed references to MPC745 CBGA package in Sections 1.3 and 1.4. Added airflow values for JA to Table 5. Corrected VIH maximum for 1.8 V mode in Table 6. Power consumption values added to Table 7. Corrected tMXRH in Table 9, deleted Note 2 application note reference. Added Max fL2CLK and Min tL2CLK values to Table 11. Updated timing values in Table 12. Corrected Note 2 of Table 13. Changed Table 14 to reflect I/F voltages supported. Removed 133 and 150 MHz columns from Table 16. Added document reference to Section 1.7. Added DBB to list of signals requiring pull-ups in Section 1.8.7. Removed log entries from Table 20 for revisions prior to public release. 2 1.8 V/2.0 V mode no longer supported; added 2.5 V support. Removed 1.8 V/2.0 V mode data from Tables 2, 3, and 6. Added 2.5 V mode data to Tables 2, 3, and 6. Extended recommended operating voltage (down to 1.8 V) for VDD, AVDD, and L2AVDD for 300 and 350 MHz parts in Table 3. Updated Table 7 and test conditions for power consumption specifications. Corrected Note 6 of Table 9 to include TLBISYNC as a mode-select signal. Updated AC timing specifications in Table 10. Updated AC timing specifications in Table 12. Corrected AC timing specifications in Table 13. Added L1_TSTCLK, L2_TSTCLK, and LSSD_MODE pull-up requirements to Section 1.8.6. Corrected Figure 22.
Table 19 provides a revision history for this hardware specification.
MPC755 RISC Microprocessor Hardware Specifications, Rev. 6.1 50 Freescale Semiconductor
Document Revision History
Table 19. Document Revision History (continued)
Rev. No. 3 Substantive Change(s) Updated format and thermal resistance specifications of Table 4. Reformatted Tables 9, 10, 11, and 12. Added dimensions A3, D1, and E1 to Figures 18, 19, and 20. Revised Section 1.8.7 and Figure 25, removed Figure 26 and Table 19 (information now included in Figure 25). Reformatted Section 1.10. Clarified address bus and address attribute pull-up recommendations in Section 1.8.7. Clarified Table 2. Updated voltage sequencing requirements in Table 1 and removed Section 1.8.3. 4 Added 450 MHz speed bin. Changed Table 16 to show 450 MHz part in example. Added row for 433 and 450 MHz core frequencies to Table 17. In Section 1.8.8, revised the heat sink vendor list. In Section 1.8.8.2, revised the interface vendor list. 5 Added Note 6 to Table 10; clarification only as this information is already documented in the MPC750 RISC Microprocessor Family User's Manual. Revised Figure 24 and Section 1.8.7. Corrected Process Identifier for 450 MHz part in Table 20. Added XPC755BRXnnnTx series to Table 21. 6 Removed 450 MHz speed grade throughout document. These devices are no longer supported for new designs; see Section 1.10.2 for more information. Relaxed voltage sequencing requirements in Notes 3 and 4 of Table 1. Corrected Note 2 of Table 7. Changed processor descriptor from `B' to `C' for 400 MHz devices and increased power specifications for full-power mode in Table 7. XPC755Bxx400LE devices are no longer produced and are documented in a separate part number specification; see Section 1.10.2 for more information. Increased power specifications for sleep mode for all speed grades in Table 7. Removed `Sleep Mode (PLL and DLL Disabled)--Typical' specification from Table 7; this is no longer tested or characterized. Added Note 4 to Table 7. Revised L2 clock duty cycle specification in Table 11 and changed Note 7. Corrected Note 3 in Table 20. Replaced Table 21 and added Tables 22 and 23. 6.1 Document template update.
MPC755 RISC Microprocessor Hardware Specifications, Rev. 6.1 Freescale Semiconductor 51
Ordering Information
10 Ordering Information
Ordering information for the devices fully covered by this specification document is provided in Section 10.1, "Part Numbers Fully Addressed by This Document." Note that the individual part numbers correspond to a maximum processor core frequency. For available frequencies, contact your local Freescale sales office. In addition to the processor frequency, the part numbering scheme also includes an application modifier which may specify special application conditions. Each part number also contains a revision code which refers to the die mask revision number. Section 10.2, "Part Numbers Not Fully Addressed by This Document," lists the part numbers which do not fully conform to the specifications of this document. These special part numbers require an additional document called a part number specification.
10.1 Part Numbers Fully Addressed by This Document
Table 20 provides the Freescale part numbering nomenclature for the MPC755 and MPC745 devices fully addressed by this document.
Table 20. Part Numbering Nomenclature
XPC Product Code XPC 2 xxx Part Identifier 755 745 755 x Process Descriptor B = HiP4DP C = HiP4DP xx Package 1 PX = PBGA RX = CBGA nnn Processor Frequency 300 350 400 x Application Modifier L: 2.0 V 100 mV 0 to 105C x Revision Level E: 2.8; PVR = 0008 3203
Notes: 1. See Section 7, "Package Description," for more information on available package types. 2. The X prefix in a Freescale part number designates a "Pilot Production Prototype" as defined by Freescale SOP 3-13. These are from a limited production volume of prototypes manufactured, tested, and Q.A. inspected on a qualified technology to simulate normal production. These parts have only preliminary reliability and characterization data. Before pilot production prototypes may be shipped, written authorization from the customer must be on file in the applicable sales office acknowledging the qualification status and the fact that product changes may still occur while shipping pilot production prototypes
10.2 Part Numbers Not Fully Addressed by This Document
Devices not fully addressed in this specification document are described in separate part number specifications which supplement and supersede this document, as described in the following tables.
Table 21. Part Numbers Addressed by XPC755BxxnnnTx Series Part Number Specification (Document Order No. MPC755BTXPNS/D)
XPC Product Code XPC 755 Part Identifier 755 B Process Descriptor B = HiP4DP xx Package RX = CBGA nnn Processor Frequency 350 400 T Application Modifier T: 2.0 V 100 mV -40 to 105C x Revision Level D: 2.7; PVR = 0008 3203 E: 2.8; PVR = 0008 3203
MPC755 RISC Microprocessor Hardware Specifications, Rev. 6.1 52 Freescale Semiconductor
Ordering Information
Table 22. Part Numbers Addressed by XPC755BxxnnnLD Series Part Number Specification (Document Order No. MPC755BLDPNS/D)
XPC Product Code XPC xxx Part Identifier 755 745 B Process Descriptor B = HiP4DP xx Package PX = PBGA RX = CBGA nnn Processor Frequency 300 350 400 L Application Modifier L: 2.0 V 100 mV 0 to 105C D Revision Level D: 2.7; PVR = 0008 3203
Table 23. Part Numbers Addressed by XPC755xxxnnnLE Series Part Number Specification (Document Order No. MPC755BLEPNS/D)
XPC Product Code XPC 755 Part Identifier 755 x Process Descriptor B = HiP4DP xx Package RX = CBGA PX = PBGA C = HiP4DP RX = CBGA 450 nnn Processor Frequency 400 L Application Modifier L: 2.0 V 100 mV 0 to 105C E Revision Level E: 2.7; PVR = 0008 3203
10.3 Part Marking
Parts are marked as the example shown in Figure 29.
XPC745B RX350LE MMMMMM ATWLYYWWA
XPC755C RX400LE MMMMMM ATWLYYWWA
745
755
BGA BGA Notes: MMMMMM is the 6-digit mask number. ATWLYYWWA is the traceability code. CCCCC is the country of assembly. This space is left blank if parts are assembled in the United States.
Figure 29. Part Marking for BGA Device
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Ordering Information
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MPC755 RISC Microprocessor Hardware Specifications, Rev. 6.1 Freescale Semiconductor 55
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MPC755EC Rev. 6.1 01/2005

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